This invention relates to semiconductor memories, a more specifically to a non-volatile random access memory cell comprised of a virtual junction field effect transistor and to arrays thereof.
In previous NVJRAMs, positive and negative voltages are used to program and erase the memory state of the cell, respectively. If both positive and negative programming voltages are to be used, then CMOS technology must be used in the peripheral circuitry fabrication. This means utilizing a more complicated fabrication process for completion of an array with peripheral circuitry on the same chip than would be required for the memory elements which are NMOS. The present invention discloses a cell similar to that described in U.S. patent application Ser. No. 228,413. A method of making this cell is described in copending application Ser. No. 264,888 filed May 18, 1981.
In the standard non-volatile JRAM cell, voltages of both positive and negative polarity are required to program and erase the memory element. The use of both polarities of voltage on a chip requires CMOS technology to implement the full devices of the array. In order to avoid the requirement for the more expensive and complicated CMOS, one alternative is to use a cell having an operating voltage of only one polarity for both programming the erasing. The use of a cell such as this would eliminate both the need for two polarities of operating voltage, and two types of semiconductor technology on the same chip. It is an object of this invention to provide a non-volatile memory cell using low voltages and having fast programming times for both write and erase states, using the same polarity of pulse voltage for both operations. It is also an object of the invention to provide a cell which is implemented in the technology that will enable peripheral devices for array cells to be built on the same substrate.